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TAS5705PAP Datasheet(PDF) 54 Page - Texas Instruments

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Part # TAS5705PAP
Description  20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
PDF  71 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5705PAP Datasheet(HTML) 54 Page - Texas Instruments

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MODULATION LIMIT REGISTER (0x10)
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)
OFFSET REGISTER (0x17)
TAS5705
SLOS549 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.
Table 17. Modulation Limit Register (0x10)
LIMIT
D7
D6
D5
D4
D3
D2
D1
D0
MIN WIDTH [DCLKs]
MODULATION LIMIT
[DCLKs]
–
–
–
–
–
0
0
0
1
2
99.2%
–
–
–
–
–
0
0
1
2
4
98.4%
–
–
–
–
–
0
1
0
3
6
97.7%
–
–
–
–
–
0
1
1
4
8
96.9%
–
–
–
–
–
1
0
0
5
10
96.1%
–
–
–
–
–
1
0
1
6
12
95.3%
–
–
–
–
–
1
1
0
7
14
94.5%
–
–
–
–
–
1
1
1
8
16
93.8%
0
0
0
0
0
–
–
–
RESERVED
Internal PWM channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 18. Channel Interchannel Delay Register Format
BITS DEFINITION
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for
0
0
0
0
0
0
0
0
channel 0 (1)
0
1
1
1
1
1
0
0
Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
0
0
Maximum negative delay, –32 × 4 DCLK cycles
0
0
Unused bits
A
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Delay = (value) × 4 DCLK cycles
0x11
0
1
0
0
1
1
0
0
Default value for channel 1 (1)
-18 ( 0XB8)
0x12
0
0
1
1
0
1
0
0
Default value for channel 2 (1)
24 ( 0X60)
0x13
0
0
0
1
1
1
0
0
Default value for channel 3 (1)
-24 ( 0XA0)
0x14
0
1
1
0
0
1
0
0
Default value for channel 4 (1)
18 ( 0X48)
0x15
1
1
0
1
0
0
0
0
Default value for channel 5 (1)
-3 ( 0XF4)
0x16
1
0
0
1
0
0
0
0
Default value for channel 6 (1)
3 ( 0X0C)
(1)
Default values are in bold.
The offset register is mapped into 0x17.
Table 19. Channel Offset Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Minimum absolute offset, 0 DCLK cycles, default for channel 0 (1)
1
1
1
1
1
1
1
1
Maximum absolute offset, 255 DCLK cycles
(1)
Default values are in bold.
54
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5705



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