Grayscale (GS) Shift Register and Data Latch

¼

¼

¼

¼

¼

¼

¼

¼

GrayscaleShiftRegister(12Bits

16Channels)

´

GrayscaleDataLatch(12Bits

16Channels)

´

SOUT

(DCSEL=L)

GSDataforOUT15

GSDataforOUT14

GSDataforOUT1

¼

GSDataforOUT0

MSB

191

180

179

12

175

11

LSB

0

OUT1-Bit0

OUT0-Bit11

OUT0-Bit0

OUT14-Bit7

(TEF)

¼

¼

OUT14-Bit7

OUT15-Bit0

(LOD-OUT4)

OUT14-Bit11

(LOD-OUT3)

OUT15-Bit11

(LOD-OUT15)

SIN

SCLK

(DCSEL=L)

¼

¼

GSDataforOUT15

GSDataforOUT14

GSDataforOUT1

¼

GSDataforOUT0

MSB

191

180

179

12

11

LSB

0

OUT0-Bit11

OUT0-Bit0

OUT15-Bit0

OUT14-Bit11

OUT15-Bit11

XLAT

(DCSEL=L)

192Bits

ToPWMTimingControlBlock

SIDDataareOverwrittenBetweenBits191and174

OUT1-Bit0

174

OUT14-Bit6

(PTW)

OUT14-Bit6

TLC5944

The grayscale (GS) shift registers and data latches are each 192 bits in length, and set the PWM timing for each

constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 28 shows the shift register

and latch configuration. Refer to Figure 14 for the timing diagram for writing data into the GS shift register and

latch.

The driver on time is controlled by the data in the GS data latch. GS data present on the SIN pin are clocked into

the GS shift register with each rising edge of the GSCLK pin when DCSEL is low. Data are shifted in MSB first.

Data are latched from the shift register into the GS data latch with a rising edge on the XLAT pin. A DCSEL level

change is allowed when SCLK is low and 100 ns after the rising edge of XLAT.

When the device powers up, the data in the GS shift register and latches are not set to any default value.

Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK

should be at a high level when powering on the device, because the constant current may be turned on as well.

All constant current output is off when BLANK is at a high level. The status information data (SID) byte is

overwritten on the most significant 18 bits of the grayscale shift register at the first rising edge of GSCLK after

XLAT goes low.

Figure 28. Grayscale Shift Register and Data Latch Configuration

Copyright © 2008, Texas Instruments Incorporated

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