AT91SAM9263 datasheet(49/1029 Pages) ATMEL

49 / 1029 page

6249B–ATARM–14-Dec-06

AT91SAM9263 Preliminary

The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an addi-

tional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-

purpose registers used to hold either data or address values. Register r14 is used as a Link

used as a program counter (PC), whereas the Current Program Status Register (CPSR) con-

tains condition code flags and the current mode bits.

In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers

(r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding

banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val-

ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when

BL or BLX instructions are executed within interrupt or exception routines. There is another

modes instead of CPSR. This register contains condition code flags and the current mode bits

saved as a result of the exception that caused entry to the current (privileged) mode.

In all modes and due to a software agreement, register r13 is used as stack pointer.

The use and the function of all the registers described above should obey ARM Procedure

Call Standard (APCS) which defines:

• constraints on the use of registers

• stack conventions

• argument passing and result return

The Thumb state register set is a subset of the ARM state set. The programmer has direct

access to:

• Eight general-purpose registers r0-r7

• Stack pointer, SP

• Link register, LR (ARM r14)

•PC

• CPSR

There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details

see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12).

11.3.7.1

Status Registers

The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The

program status registers:

• hold information about the most recently performed ALU operation

• control the enabling and disabling of interrupts

• set the processor operation mode

AT91SAM9263 Datasheet(PDF) 49 Page - ATMEL Corporation