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ST72F321BAR7TCRE Datasheet(PDF) 48 Page - STMicroelectronics |
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ST72F321BAR7TCRE Datasheet(HTML) 48 Page - STMicroelectronics |
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48 / 247 page  Supply, reset and clock management ST72321Bxxx-Auto 48/247 The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 19: Electrical characteristics. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 13), the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 6.5.3 External power-on RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency (see Section 19.3: Operating conditions on page 193). A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.5.4 Internal low voltage detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: ● Power-on RESET ● Voltage drop RESET The device RESET pin acts as an output that is pulled low when VDD <VIT+ (rising edge) or VDD <VIT- (falling edge) as shown in Figure 13. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 6.5.5 Internal watchdog RESET The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 13. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. |
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