33911 datasheet(27/45 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33911

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

RST Wake-up

While in Stop Mode, the 33911 can wake-up when the

RST pin is held low long enough to pass the internal glitch

filter. Then, it will change to Normal Request or Normal

Modes depending on the WDCONF pin configuration. The

RST wake-up does not generate an interrupt and is not

reported via the SPI.

From Stop Mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• CS wake-up

• LIN wake-up

• RST wake-up

From Sleep Mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• LIN wake-up

WINDOW WATCHDOG

The 33911 includes a configurable window watchdog

which is active in Normal Mode. The watchdog can be

configured by an external resistor connected to the WDCONF

pin. The resistor is used to achieve higher precision in the

timebase used for the watchdog.

SPI clears are performed by writing through the SPI in the

MOD bits of the Mode Control Register (MCR).

During the first half of the SPI timeout, watchdog clears are

not allowed, but after the first half of the SPI timeout window,

the clear operation opens. If a clear operation is performed

outside the window, the 33911 will reset the MCU, in the

same way as when the watchdog overflows.

Figure 16. Window Watchdog Operation

To disable the watchdog function in Normal Mode, the

user must connect the WDCONF pin to ground. This

measure effectively disables Normal Request Mode. The

WDOFF bit in the Watchdog Status Register (WDSR) will be

set. This condition is only detected during Reset Mode.

If neither a resistor nor a connection to ground is detected,

the watchdog falls back to the internal lower precision

timebase of 150ms (typ.) and signals the faulty condition

through the WDSR.

The watchdog timebase can be further divided by a

prescaler which can be configured by the Timing Control

window watchdog is not active but there is a 150ms (typ.)

timeout for leaving the Normal Request Mode. In case of a

timeout, the 33911 will enter into Reset Mode, resetting the

microcontroller before entering again into Normal Request

Mode.

HIGH SIDE OUTPUT PIN HS1

This output is one high side driver intended to drive small

resistive loads or LEDs incorporating the following features:

• PWM capability (software maskable)

• Open-load detection

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• High-voltage shutdown (software maskable)

• Cyclic sense

The high side switch is controlled by the HS1 bit in the High

Side Control Register (HSCR).

PWM Capability (direct access)

The high side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

If the HS1 bit and PWMHS1 is set in the HSCR, then the

HS1 driver is turned on if the PWMIN pin is high, and turned

off if the PWMIN pin is low.

WD PERIOD (tPWD)

WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

WD TIMING X 50%

WD TIMING SELECTED BY REGISTER

ON WDCONF PIN

33911 Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc

33911 Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc

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