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33911 Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc |
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33911 Datasheet(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 45 page ![]() Analog Integrated Circuit Device Data 40 Freescale Semiconductor 33911 FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Interrupt Mask Register - IMR This register allow to mask some of interrupt sources. The respective flags within the Interrupt Source Register (ISR) will continue to work but will not generate interrupts to the MCU. The 5V Regulator over-temperature prewarning interrupt and Under Voltage (VSUV) interrupts can not be masked and will always cause an interrupt. Writing to the Interrupt Mask Register (IMR) will return the ISR. HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled LSM - Low Side Interrupt Mask This write-only bit enables/disables interrupts generated in the low side block. 1 = LS Interrupts Enabled 0 = LS Interrupts Disabled LINM - LIN Interrupts Mask This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled VMM - Voltage Monitor Interrupt Mask This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor Block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Interrupt Source Register - ISR This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10µs and then be driven low again. This register is also returned when writing to the IMR. ISRx - Interrupt Source Register These read-only bits indicate the interrupt source following Table 30. If no interrupt is pending than all bits are 0. In case more than one interrupt is pending, than the interrupt sources are handled sequentially multiplex. Table 30. Interrupt Sources Table 28. Interrupt Mask Register - $E C3 C2 C1 C0 Write HSM LSM LINM VMM Reset Value 1111 Reset Condition POR Table 29. Interrupt Source Register - $E/$F S3 S2 S1 S0 Read ISR3 ISR2 ISR1 ISR0 Interrupt Source Priority ISR3 ISR2 ISR1 ISR0 none maskable maskable 0 0 0 0 no interrupt no interrupt none 0 0 0 1 Lx Wake-up from Stop Mode- highest 0 0 1 0 - HS Interrupt (Over-temperature) 0 0 1 1 - LS Interrupt (Over-temperature) 0 1 0 0 LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN OC) or LIN Wake-up 0 1 0 1 Voltage Monitor Interrupt (Low-voltage and VDD over-temperature) Voltage Monitor Interrupt (High-voltage) 0 1 1 0 - Forced Wake-up lowest |
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