MSC8122 datasheet(37/48 Pages) FREESCALE

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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

2.5.12

EE Signals

Figure 28 shows the signal behavior of the EE pins.

2.5.13

JTAG Signals

Figure 27. GPIO Timing

Table 29. EE Pin Timing

Number

Characteristics

Type

Min

EE0 (input)

Asynchronous

4 core clock periods

EE1 (output)

Synchronous to Core clock

1 core clock period

Notes:

The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.

Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 28. EE Pin Timing

Table 30. JTAG Timing

No.

Characteristics

All

frequencies

Unit

Min

Max

700

TCK frequency of operation (1/(T

C ×

4); maximum 25 MHz)

0.0

MHz

701

TCK cycle time

40.0

—

702

TCK clock pulse width measured at VM = 1.6 V

•High

•Low

20.0

16.0

—

703

TCK rise and fall times

0.0

3.0

REFCLK

GPIO

(Output)

GPIO

(Input)

Valid

603

High Impedance

604

605

602

601

EE1 out

EE0 in

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