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4501 Datasheet(PDF) 38 Page - Renesas Technology Corp |
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4501 Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 116 page ![]() Rev.3.01 2005.02.07 page 38 of 112 REJ03B0104-0301 4501 Group Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation Name D0, D1 D2/C, D3/K P00, P01, P02, P03 P10, P11, P12/CNTR, P13/INT P20/AIN0, P21/AIN1 Notes 1: Output latch is set to “1.” 2: Pull-up transistor is turned OFF. Function D0, D1 D2, D3 P00–P03 P10–P13 P20, P21 State High-impedance (Note 1) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) (1) Power-on reset Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Table 14 Port state at reset RESET pin WEF Watchdog reset signal (Note 1) Pull-up transistor (Note 1) Power-on reset circuit Volgate drop detection circuit VDD (Note 3) 100 µs or less (Note 2) Internal reset signal Power-on Reset released Internal reset signal Reset state Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Power-on reset circuit output |
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