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4501 Datasheet(PDF) 45 Page - Renesas Technology Corp |
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4501 Datasheet(HTML) 45 Page - Renesas Technology Corp |
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45 / 116 page  4501 Group Rev.3.01 2005.02.07 page 45 of 112 REJ03B0104-0301 PU03 PU02 PU01 PU00 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained 0 1 0 1 0 1 0 1 W Table 18 Pull-up control register and interrupt control register PU13 PU12 PU11 PU10 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit Pull-up control register PU1 at reset : 00002 at RAM back-up : state retained 0 1 0 1 0 1 0 1 W PU23 PU22 PU21 PU20 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 pull-up transistor control bit Pull-up control register PU2 at reset : 00002 at RAM back-up : state retained 0 1 0 1 0 1 0 1 W I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin timer 1 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in- struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction. Interrupt control register I1 R/W at RAM back-up : state retained at reset : 00002 INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled 0 1 0 1 0 1 0 1 |
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