HD64F36078G datasheet(63/564 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Sep. 10, 2007 Page 31 of 528

REJ09B0216-0300

(2)

@ERn

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of

which contain the address of the operand on memory.

(3)

@(d:16, ERn) or @(d:24, ERn)

A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the lower 24 bits of the sum the address of a

memory operand. A 16-bit displacement is sign-extended when added.

(4)

@ERn+ or @-ERn

(a)

@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word

or longword access, the register value should be even.

(b)

@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result is the address of a memory operand.

The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for

word access, or 4 for longword access. For the word or longword access, the register value

should be even.

(5)

Absolute Address

@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit

absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the

entire address space.

Table 2.11 shows the access ranges of absolute addresses according to the modes of operation of

each product group.

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