HD64F36078G datasheet(91/564 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 Sep. 10, 2007 Page 59 of 528

REJ09B0216-0300

Stack area

SP - 4

SP - 3

SP - 2

SP - 1

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4

CCR

CCR*

PCH

PCL

Prior to start of interrupt

exception handling

After completion of interrupt

exception handling

Even address

[Legend]

Normal mode operation

PCE:

PCH:

PCL:

CCR:

SP:

Bits 23 to 16 of program counter (PC)

Bits 15 to 8 of program counter (PC)

Bits 7 to 0 of program counter (PC)

Condition code register

Stack pointer

Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine.

2. Register contents must always be saved and restored in word units, starting from an even-numbered address.

Ignored when returning from the interrupt handling routine.

PC and CCR

saved to stack

Stack area

SP - 4

SP - 3

SP - 2

SP - 1

SP (R7)

SP + 1

SP + 2

SP + 3

SP + 4

CCR

PCE

PCH

PCL

Prior to start of interrupt

exception handling

After completion of interrupt

exception handling

Even address

PC and CCR

saved to stack

Advanced mode operation

Figure 3.2 Stack Status after Exception Handling

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