SH7261 datasheet(66/1348 Pages) RENESAS

66 / 1348 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 34 of 1312

REJ09B0320-0200

2.3.2

Addressing Modes

Addressing modes and effective address calculation are as follows:

Table 2.8

Addressing Modes and Effective Addresses

Addressing Mode

Instruction Format

Effective Address Calculation

Equation

The effective address is register Rn.

(The operand is the contents of register Rn.)

—

@Rn

The effective address is the contents of register

Rn.

with post-increment

@Rn+

The effective address is the contents of register

Rn. A constant is added to the contents of Rn

after the instruction is executed. 1 is added for a

byte operation, 2 for a word operation, and 4 for

a longword operation.

1/2/4

Rn + 1/2/4

(After instruction

execution)

Byte:

Rn + 1

→ Rn

Word:

Rn + 2

→ Rn

Longword:

Rn + 4

→ Rn

with pre-decrement

@-Rn

The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted

for a byte operation, 2 for a word operation, and

4 for a longword operation.

1/2/4

Rn – 1/2/4

–

Rn – 1/2/4

Byte:

Rn – 1

→ Rn

Word:

Rn – 2

→ Rn

Longword:

Rn – 4

→ Rn

(Instruction is

executed with

Rn after this

calculation)

SH7261 Datasheet(PDF) 66 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 66 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL