SH7261 datasheet(102/1348 Pages) RENESAS

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Section 3 Floating-Point Unit (FPU)

Rev. 2.00 Sep. 07, 2007 Page 70 of 1312

REJ09B0320-0200

N = 1: sNaN

N = 0: qNaN

11111111

Nxxxxxxxxxxxxxxxxxxxxxx

Figure 3.3 Single-Precision NaN Bit Pattern

An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point

value.

• When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.

• When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this

case, the contents of the operation destination register are unchanged.

If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been

input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit

in FPSCR. An exception will not be generated in this case.

The qNAN values as operation results are as follows:

• Single-precision qNaN: H'7FBF FFFF

• Double-precision qNaN: H'7FF7 FFFF FFFF FFFF

See the individual instruction descriptions for details of floating-point operations when a non-

number (NaN) is input.

3.2.3

Denormalized Numbers

For a denormalized number floating-point value, the exponent field is expressed as 0, and the

fraction field as a non-zero value.

In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a

denormalized number (source operand or operation result) is always flushed to 0 in a floating-

point operation that generates a value (an operation other than copy, FNEG, or FABS).

When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is

processed as it is. See the individual instruction descriptions for details of floating-point

operations when a denormalized number is input.

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