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SH7261 Datasheet(PDF) 110 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 110 Page - Renesas Technology Corp |
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110 / 1348 page ![]() Section 4 Clock Pulse Generator (CPG) Rev. 2.00 Sep. 07, 2007 Page 78 of 1312 REJ09B0320-0200 Figure 4.1 shows a block diagram of the clock pulse generator. CKIO PLL circuit 2 ( ×2, 4) EXTAL XTAL MD_CLK1 MD_CLK0 FRQCR STBCR STBCR2 STBCR3 STBCR4 STBCR5 PLL circuit 1 ( ×1, 2, 3, 4, 6, 8) Crystal oscillator Peripheral bus Bus interface CPG control unit Clock frequency control circuit Standby control circuit On-chip oscillator ×1 ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 ×1/12 Divider Internal clock (I φ, Max. : 120 MHz (Regular specifications), 100 MHz (Wide-range specifications)) Peripheral clock (P φ, Max. 40 MHz) Bus clock (B φ = CKIO, Max. 60 MHz) FRQCR: STBCR: STBCR2: STBCR3: STBCR4: STBCR5: [Legend] Frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Figure 4.1 Block Diagram of Clock Pulse Generator |
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