SH7261 datasheet(222/1348 Pages) RENESAS

222 / 1348 page

Section 8 Cache

Rev. 2.00 Sep. 07, 2007 Page 190 of 1312

REJ09B0320-0200

8.2

The cache has the following registers.

Table 8.2

Abbreviation

R/W

Initial Value

Address

Access Size

Cache control register 1

CCR1

R/W

H'00000000

H'FFFC1000

Cache control register 2

CCR2

R/W

H'00000000

H'FFFC1004

8.2.1

Cache Control Register 1 (CCR1)

The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all

instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF

bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or

write-back mode for operand cache.

Programs that change the contents of CCR1 should be placed in an address space that is not

cached, and an address space that is cached should be accessed after reading the contents of

CCR1.

CCR1 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a

manual reset or in software standby mode.

987654321

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:











ICF

ICE

OCF

OCE

SH7261 Datasheet(PDF) 222 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 222 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL