SH7606 datasheet(28/532 Pages) RENESAS

28 / 532 page

Section 1 Overview

Rev. 4.00 Sep. 13, 2007 Page 2 of 502

REJ09B0239-0400

User break controller (UBC):

• Address, data value, access type, and data size are available for setting as break conditions

• Supports the sequential break function

• Two break channels

U memory:

• 4 kbytes

Cache memory:

• Unified cache, mixture of instructions and data

• 4-way set associative type

• Selection of write-back or write-through mode

• 16 Kbytes

Bus state controller (BSC):

• Address space is divided into five areas: three areas 0, 3, and 4; each a maximum of 64

Mbytes, and two areas 5B and 6B; each a maximum of 32 Mbytes (address map 1 mode).

• Address space is divided into five areas, 0, 3, 4, 5, and 6; each a maximum of 64 Mbytes

(address map 2 mode).

• 16-bit external bus

• The following features are settable for each area.

 Bus size (8 or 16 bits)

 Number of access wait cycles

 Setting of idle wait cycles

 Specifying the memory to be connected to each area enables direct connection to SRAM,

SDRAM, and PCMCIA.

 Outputs chip select signals (CS0, CS3, CS4, CS5B, and CS6B) for corresponding area

• SDRAM refresh function

 Supports auto-refresh and self-refresh modes

• SDRAM burst access function

• PCMCIA access function

 Conforms to the JEIDA Ver. 4.2 standard, two slots

• Selection of big or little endian mode (The mode of all the areas is switched collectively by a

mode pin.)

SH7606 Datasheet(PDF) 28 Page - Renesas Technology Corp