SH7065 datasheet(49/941 Pages) RENESAS

49 / 941 page

Section 2 CPU

Rev. 5.00 Sep 11, 2006 page 27 of 916

REJ09B0332-0500

MACL

MACH

Multiply and accumulate

Procedure register (PR)

Program counter (PC)

Figure 2.3 System Register Configuration

In the SH7065, of the DSP unit registers (DSP registers) described below, the DSP status register

(DSR) and five of the eight data registers (A0, X0, X1, Y0, and Y1) are treated as system

registers. A0 is a 40-bit register, but when data is output from the A0 register the guard bit field

(A0G) is ignored, and when data is input to the A0 register the MSB is copied into the guard bit

field (A0G).

2.1.4

DSP Registers

The DSP unit has eight data registers and one control register as DSP registers.

The DSP data registers comprise two 40-bit registers, A0 and A1, and six 32-bit registers, M0,

M1, X0, X1, Y0, and Y1. Registers A0 and A1 each have an 8-bit guard bit field, designated A0G

and A1G, respectively.

The DSP data registers are used as DSP instruction operands in DSP data transfer and processing.

Instructions that access the DSP data registers are of three types, for DSP data processing, and X

and Y data transfer processing.

The control register is the 32-bit DSP status register (DSR), which shows operation results. The

DSR register contains bits that indicate the result of an operation—the Signed Greater Than bit

(GT), Zero Value bit (Z), Negative Value bit (N), Overflow bit (V), and DSP Condition bit

(DC)—and also Condition Select bits (CS) that control the DC bit setting.

The DC bit is a status flag that closely resembles the T bit of the SuperH microcomputer CPU

core. In the case of a conditional DSP type instruction, execution during DSP data processing is

controlled in accordance with the DC bit. This control extends only to DSP unit execution, and

only DSP registers are updated. It has no effect on address calculation or SuperH microcomputer

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