SH7065 datasheet(22/941 Pages) RENESAS

22 / 941 page

Rev. 5.00 Sep 11, 2006 page xxii of xxii

22.3.3 Bus Timing........................................................................................................... 800

22.3.4 Direct Memory Access Controller Timing........................................................... 815

22.3.5 16-Bit Timer Pulse Unit (TPU) Timing ............................................................... 818

22.3.6 Motor Management Timer (MMT) Timing ......................................................... 819

22.3.7 Port Output Enable (POE) Timing....................................................................... 820

22.3.8 I/O Port Timing.................................................................................................... 821

22.3.9 Watchdog Timer Timing...................................................................................... 822

22.3.10 Serial Communication Interface Timing .............................................................. 822

22.3.11 A/D Conversion Timing....................................................................................... 824

22.3.12 A/D Conversion Characteristics........................................................................... 826

22.3.13 D/A Conversion Characteristics........................................................................... 827

Appendix A On-Chip Peripheral Module Registers.................................................. 829

Appendix B Pin States ....................................................................................................... 849

B.1

Pin States in Reset, Power-Down State, and Bus-Released State...................................... 849

B.2

Bus-Related Signal Pin States ........................................................................................... 853

Appendix C I/O Port Block Diagrams........................................................................... 862

Appendix D Restrictions and Caution on HD64F7065S

(and HD64F7065A Lots Prior to “1D5”)............................................. 910

D.1

BSC Restrictions ............................................................................................................... 910

D.2

Restrictions in Case of Contention between DSP Instruction and DMAC Transfer.......... 910

D.3

Pin State Related Restrictions ........................................................................................... 911

D.4

Caution Concerning Electrical Characteristics.................................................................. 911

D.5

DMAC Restrictions........................................................................................................... 911

D.6

Restrictions about Changing the Saturation Operation Mode during the Execution

of Multiply/Multiply and Accumulate, or DSP Instructions.............................................. 912

Appendix E Product Lineup............................................................................................. 914

Appendix F Package Dimensions................................................................................... 915

SH7065 Datasheet(PDF) 22 Page - Renesas Technology Corp