SH7065 datasheet(7/941 Pages) RENESAS

7 / 941 page

Rev. 5.00 Sep 11, 2006 page vii of xxii

Main Revisions for This Edition

Item

Page

Revision (See Manual for Details)

All

—

• Notification of change in company name amended

(Before) Hitachi, Ltd.

→ (After) Renesas Technology Corp.

9.3.4 Types of DMA

Transfer

Relationship between

DMA Transfer Type,

Request Mode, and Bus

Mode

Table 9.6 Relationship

between DMA Transfer

Type, Request Mode,

and Bus Mode

340

Table amended

Address

Mode

Type of Transfer

Request

Mode

Bus

Mode

Transfer

Size (Bits)

Usable

Channels

Dual

External memory and external memory

Any*

B/C

8/16/32

0–3

External memory and memory-mapped

external device

Any*

B/C

8/16/32

0–3

Memory-mapped external device and

memory-mapped external device

Any*

B/C

8/16/32

0–3

External memory and on-chip memory

Any*

B/C

8/16/32

0–3

External memory and on-chip

peripheral module

Any*

B/C

8/16/32*

0–3

Memory-mapped external device and

on-chip memory

Any*

B/C

8/16/32

0–3

Memory-mapped external device and

on-chip peripheral module

Any*

B/C

8/16/32*

0–3

On-chip memory and on-chip memory

Any*

B/C

8/16/32

0–3

On-chip memory and on-chip peripheral

module

Any*

B/C

8/16/32*

0–3

On-chip peripheral module and on-chip

peripheral module

Any*

B/C

8/16/32*

0–3

11.6 Usage Notes

484

Description added

Pay Attention to the Notices Below, When a Value Is Written

into the Timer General Register U (TGRU), Timer General

Case of Written into Free Operation Address (*):

…

Writing Operation into Timer Period Data Register (TPDR) and

Timer Dead Time Data Register (TDDR) When MMT Is

Operating:

…

Notes on Halting TCNT Counter Operation:

…

15.7.2 Handling of

Analog Input Pins

Figure 15.8 Example

of Analog Input Pin

Protection Circuit

Figure 15.9 Analog

Input Pin Equivalent

Circuit

Table 15.5 Analog

Input Pin

Specifications

619, 620 Description of preliminary deleted

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