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SH7052 Datasheet(PDF) 389 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 389 Page - Renesas Technology Corp

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OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to
H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when
the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is
H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input.
When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the
next DCNT input clock is input.
The timing in this case is shown in figure 10.40.
CK
DCNT
DCNT input clock
Underflow signal
Interrupt status flag
OSF
Interrupt request signal
OSI
H'0001
H'0000
H'0000
Figure 10.40 OSF Setting Timing in Underflow



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