SH7052 datasheet(20/919 Pages) RENESAS

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16.4.5 A/D Converter Activation by ATU-II .................................................................. 586

16.5

Interrupt Sources and DMA Transfer Requests ................................................................ 586

16.6

Usage Notes ....................................................................................................................... 586

16.6.1 A/D conversion accuracy definitions ................................................................... 588

Section 17 Advanced User Debugger (AUD) ............................................................. 591

17.1

Overview............................................................................................................................ 591

17.1.1 Features ................................................................................................................ 591

17.1.2 Block Diagram...................................................................................................... 592

17.2

Pin Configuration .............................................................................................................. 592

17.2.1 Pin Descriptions ................................................................................................... 593

17.3

Branch Trace Mode ........................................................................................................... 595

17.3.1 Overview .............................................................................................................. 595

17.3.2 Operation .............................................................................................................. 595

17.4

RAM Monitor Mode.......................................................................................................... 597

17.4.1 Overview .............................................................................................................. 597

17.4.2 Communication Protocol...................................................................................... 597

17.4.3 Operation .............................................................................................................. 598

17.5

Usage Notes ....................................................................................................................... 599

17.5.1 Initialization.......................................................................................................... 599

17.5.2 Operation in Software Standby Mode .................................................................. 599

17.5.3 ROM Area Writes ................................................................................................ 600

Section 18 Pin Function Controller (PFC).................................................................... 601

18.1

Overview............................................................................................................................ 601

18.2

Register Configuration ...................................................................................................... 606

18.3

Register Descriptions......................................................................................................... 607

18.3.1 Port A IO Register (PAIOR) ................................................................................ 607

18.3.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 607

18.3.3 Port B IO Register (PBIOR)................................................................................. 612

18.3.4 Port B Control Registers H and L (PBCRH, PBCRL) ......................................... 612

18.3.5 Port B Invert Register (PBIR) .............................................................................. 618

18.3.6 Port C IO Register (PCIOR)................................................................................. 619

18.3.7 Port C Control Register (PCCR) .......................................................................... 620

18.3.8 Port D IO Register (PDIOR) ................................................................................ 622

18.3.9 Port D Control Registers H and L (PDCRH, PDCRL) ........................................ 623

18.3.10 Port E IO Register (PEIOR) ................................................................................. 627

18.3.11 Port E Control Register (PECR)........................................................................... 628

18.3.12 Port F IO Register (PFIOR).................................................................................. 633

18.3.13 Port F Control Registers H and L (PFCRH, PFCRL) .......................................... 634

18.3.14 Port G IO Register (PGIOR) ................................................................................ 640

18.3.15 Port G Control Register (PGCR).......................................................................... 641

18.3.16 Port H IO Register (PHIOR) ................................................................................ 643

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