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SH7052 Datasheet(PDF) 98 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 98 Page - Renesas Technology Corp |
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98 / 919 page  72 5.6 When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Bus Error Interrupt FPU Exception Immediately after a delayed branch instruction* 1 Not accepted Not accepted Not accepted Immediately after an interrupt-disabled instruction* 2 Not accepted* 3 Not accepted Accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L 3. In the SH-2 a bus error is accepted. |
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