SH7052 datasheet(466/919 Pages) RENESAS

466 / 919 page

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• Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin

(external)

• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full

interrupts can start the direct memory access controller (DMAC) to transfer data.

• Selection of LSB-first or MSB-first transfer (8-bit length)

This selection is available regardless of the communication mode. (The descriptions in this

section are based on LSB-first transfer.)

14.1.2

Block Diagram

Figure 14.1 shows a block diagram of the SCI.

Parity

generation

Parity check

Transmit/

receive control

Baud rate

generator

Clock

External clock

Internal

data bus

RxD

RDR

TDR

RSR

TSR

SSR

SCR

SMR

SDCR

BRR

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

SCK

RSR:

RDR:

TSR:

TDR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

SMR:

SCR:

SSR:

BRR:

SDCR:

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial direction control register

TxD

SCI

Module data bus

Figure 14.1 SCI Block Diagram

SH7052 Datasheet(PDF) 466 Page - Renesas Technology Corp

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