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SH7052 Datasheet(PDF) 659 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 659 Page - Renesas Technology Corp |
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659 / 919 page ![]() 633 18.3.12 Port F IO Register (PFIOR) Bit: 15 14 13 12 11 10 9 8 PF15 IOR PF14 IOR PF13 IOR PF12 IOR PF11 IOR PF10 IOR PF9 IOR PF8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PF7 IOR PF6 IOR PF5 IOR PF4 IOR PF3 IOR PF2 IOR PF1 IOR PF0 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port F. Bits PF15IOR to PF0IOR correspond to pins PF15/ BREQ to PF0/A16. PFIOR is enabled when port F pins function as general input/output pins (PF15 to PF0), and disabled otherwise. When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0. PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. |
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