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SH7052 Datasheet(PDF) 666 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 666 Page - Renesas Technology Corp |
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666 / 919 page  640 18.3.14 Port G IO Register (PGIOR) Bit: 15 14 13 12 11 10 9 8 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — PG3IOR PG2IOR PG1IOR PG0IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output direction of the 4 pins in port G. Bits PG3IOR to PG0IOR correspond to pins PG3/ IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When port G pins function as PG3 to PG0, a pin becomes an output when the corresponding bit in PGIOR is set to 1, and an input when the bit is cleared to 0. PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. |
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