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SH7052 Datasheet(PDF) 739 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 739 Page - Renesas Technology Corp |
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739 / 919 page  713 Table 20.8 Program/Program-Verify Parameter Flow Section Item Symbol Min Typ Max Unit Notes Program/ program-verify Wait time after PSU1 bit setting t SPSU 50 50 — µs Wait time after P1 bit setting (10µs) t SP10 810 12 µs Additional- programming time wait Wait time after P1 bit setting (30µs) t SP30 28 30 32 µs Programming time wait Wait time after P1 bit setting (200µs) t SP200 198 200 202 µs Programming time wait Wait time after P1 bit clearing t CP 55 — µs Wait time after PSU1 bit clearing t CPSU 55 — µs Wait time after PV1 bit setting t SPV 44 — µs Wait time after dummy write t SPVR 22 — µs Wait time after PV1 bit clearing t CPV 22 — µs All Wait time after SWE1 bit setting t SSWE 11 — µs Wait time after SWE1 bit clearing t CSWE 100 100 — µs 20.7.3 Erase Mode When erasing flash memory, the erase/erase-verify flowchart (single-block erase) shown in figure 20.15 should be followed for each block. To perform data or program erasure, set the SWE1 bit to 1 in flash memory control register n (FLMCR1), then, after an interval of t SSWE or longer, make a 1-bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1, EBR2). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set 19.8 ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU1 bit in FLMCR1, and after an interval of t SESU or longer, the operating mode is switched to erase mode by setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed t SE. |
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