SH7052 datasheet(791/919 Pages) RENESAS

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765

End of erasing

Start

Set SWE1 bit in FLMCR1

Set ESU1 bit in FLMCR1

Set E1 bit in FLMCR1

Wait: tSSWE

Wait: tSESU

n = 1

Set EBR1, 2

Enable WDT

Wait: tSE

Wait: tCE

Wait: tCESU

Wait: tSEV

Set block start address to verify address

Wait: tSEVR

Wait: tCEV

Start erase

Clear E1 bit in FLMCR1

Clear ESU1 bit in FLMCR1

Set EV1 bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV1 bit in FLMCR1

Wait: tCEV

Clear EV1 bit in FLMCR1

Wait: tCSWE

Disable WDT

Halt erase

Verify data = all "1"?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Wait: tCSWE

Clear SWE1 bit in FLMCR1

≥ 100?

← n + 1

Increment

address

Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.

2. Verify data is read in 32-bit (longword) units.

3. Set only one bit in EBR1. More than one bit cannot be set.

4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.

Erasing must be performed

in block units.

Figure 21.15 Erase/Erase-Verify Flowchart

SH7052 Datasheet(PDF) 791 Page - Renesas Technology Corp

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