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SH7052 Datasheet(PDF) 907 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 907 Page - Renesas Technology Corp |
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907 / 919 page  881 A.2 Register States in Reset and Power-Down States Table A.2 Register States in Reset and Power-Down States Reset State Power-Down State Type Name Power-On Hardware Standby Software Standby Sleep CPU R0 to R15 Initialized Initialized Held Held SR GBR VBR MACH, MACL PR PC Interrupt controller IPRA, IPRC to IPRL Initialized Initialized Held Held (INTC) IOR ISR User break controller UBARH, UBARL Initialized Initialized Held Held (UBC) UBAMRH, UBAMRL UBBR UBCR Bus state controller BCR1, BCR2 Initialized Initialized Held Held (BSC) WCR Direct memory access SAR0 to SAR3 Undefined Undefined Undefined Held controller (DMAC) DAR0 to DAR3 DMATCR0 to DMATCR3 CHCR0 to CHCR3 Initialized Initialized Initialized DMAOR Advanced timer unit-II (ATU-II) BFR6A to BFR6D, BFR7A to BFR7D Initialized Initialized Initialized Held CYLR6A to CYLR6D, CYLR7A to CYLR7D DCNT8A to DCNT8P DSTR |
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