SH7052 datasheet(143/919 Pages) RENESAS

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117

8.1.3

Pin Configuration

Table 8.1 shows the bus state controller pin configuration.

Table 8.1

Pin Configuration

Name

Abbr.

I/O

Description

Address bus

A21 to A0

Address output

Data bus

D15 to D0

I/O

16-bit data bus

Chip select

CS0 to CS3

Chip select signals indicating the area being

accessed

Read

Strobe that indicates the read cycle for ordinary

space/multiplex I/O

Upper write

WRH

Strobe that indicates a write cycle to the upper 8 bits

(D15 to D8)

Lower write

WRL

Strobe that indicates a write cycle to the lower 8 bits

(D7 to D0)

Wait

WAIT

Wait state request signal

Bus request

BREQ

Bus release request input

Bus acknowledge

BACK

Bus use enable output

Note:

When an 8-bit bus width is selected for external space,

WRL is enabled.

When a 16-bit bus width is selected for external space,

WRH and WRL are enabled.

8.1.4

The BSC has four registers. These registers are used to control wait states, bus width, and

interfaces with memories like ROM and SRAM, as well as refresh control. The register

configurations are listed in table 8.2.

All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware

standby mode. Values are retained in a manual reset and in software standby mode.

SH7052 Datasheet(PDF) 143 Page - Renesas Technology Corp

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