SH7052 datasheet(211/919 Pages) RENESAS

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185

Table 10.3

ATU-II Registers (cont)

Channel

Name

Abbrevia-

tion

R/W

Initial

Value

Address

Access Size (Bits)

Output compare

OCR2G

R/W

H'FFFF H'FFFFF620

Output compare

OCR2H

R/W

H'FFFF H'FFFFF622

Offset base register 2

OSBR2

H'0000 H'FFFFF624

Timer I/O control

TIOR2A

R/W

H'00

H'FFFFF627

8, 16

Timer I/O control

TIOR2B

R/W

H'00

H'FFFFF626

Timer I/O control

TIOR2C

R/W

H'00

H'FFFFF629

Timer I/O control

TIOR2D

R/W

H'00

H'FFFFF628

Timer control register

TCR2A

R/W

H'00

H'FFFFF62B

Timer control register

TCR2B

R/W

H'00

H'FFFFF62A

Timer status register

TSR2A

R/(W)* H'0000 H'FFFFF62C 16

Timer status register

TSR2B

R/(W)* H'0000 H'FFFFF62E

Timer interrupt enable

TIER2A

R/W

H'0000 H'FFFFF630

Timer interrupt enable

TIER2B

R/W

H'0000 H'FFFFF632

3 to 5

Timer status register 3

TSR3

R/(W)* H'0000 H'FFFFF480

Timer interrupt enable

TIER3

R/W

H'0000 H'FFFFF482

Timer mode register

TMDR

R/W

H'00

H'FFFFF484

Free-running counter 3 TCNT3

R/W

H'0000 H'FFFFF4A0 16

General register 3A

GR3A

R/W

H'FFFF H'FFFFF4A2

General register 3B

GR3B

R/W

H'FFFF H'FFFFF4A4

General register 3C

GR3C

R/W

H'FFFF H'FFFFF4A6

General register 3D

GR3D

R/W

H'FFFF H'FFFFF4A8

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