R8C16 datasheet(92/279 Pages) RENESAS

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R8C/16 Group, R8C/17 Group

12. Watchdog Timer

Rev.2.10

Jan 19, 2006

Page 79 of 254

REJ09B0169-0210

Figure 12.2

OFS and WDC Registers

Watchdog Timer Control Register

Symbol

Address

After Reset

WDC

000Fh

00011111b

Bit Symbol

Bit Name

Function

b3 b2 b1 b0

High-order Bit of Watchdog Timer

—

(b4-b0)

—

(b5)

b7 b6 b5 b4

Reserved Bit

Set to “0”

WDC7

—

(b6)

Reserved Bit

Set to “0”

Prescaler Select Bit

0 : Divide-by-16

1 : Divide-by-128

Option Function Select Register

(1)

Symbol

Address

Before Shipment

OFS

0FFFFh

FFh(2)

Bit Symbol

Bit Name

Function

NOTES :

2. If the block including the OFS register is erased, “FFh” is set to the OFS register.

CSPROINI

Count Source Protection

Mode After Reset Select

Bit

0 : Count source protect mode enabled after reset

1 : Count source protect mode disabled after reset

ROM Code Protect Bit

0 : ROM code protect enabled

1 : ROM code protect disabled

—

(b6-b4)

Reserved Bit

Set to “1”

The OFS register is on the flash memory. Write to the OFS register w ith a program.

—

(b1)

Reserved Bit

Set to “1”

ROMCR

ROM Code Protect

Disabled Bit

0 : ROM code protect disabled

1 : ROMCP1 enabled

ROMCP1

WDTON

Watchdog Timer Start

Select Bit

0 : Watchdog timer starts automatically after reset

1 : Watchdog timer is inactive after reset

111

b7 b6 b5 b4 b3 b2 b1 b0

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