SH7641 datasheet(22/1040 Pages) RENESAS

22 / 1040 page

Rev. 2.00 Mar. 15, 2007 Page xxii of l

18.7.8 Conflict between TGR Read and Input Capture ................................................... 634

18.7.9 Conflict between TGR Write and Input Capture .................................................. 635

18.7.10 Conflict between Buffer Register Write and Input Capture.................................. 636

18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection ........... 636

18.7.12 Counter Value during Complementary PWM Mode Stop .................................... 638

18.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 638

18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 639

18.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 640

18.7.16 Conflict between Overflow/Underflow and Counter Clearing ............................. 640

18.7.17 Conflict between TCNT Write and Overflow/Underflow .................................... 641

18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to

Reset-Synchronous PWM Mode........................................................................... 642

18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous

PWM Mode .......................................................................................................... 642

18.7.20 Interrupts in Module Standby Mode ..................................................................... 642

18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in

Cascade Connection.............................................................................................. 642

18.8

MTU Output Pin Initialization........................................................................................... 643

18.8.1 Operating Modes .................................................................................................. 643

18.8.2 Reset Start Operation ............................................................................................ 643

18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 644

18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of

Error during Operation, etc. .................................................................................. 645

18.9

Port Output Enable (POE) ................................................................................................. 675

18.9.1 Features................................................................................................................. 675

18.9.2 Pin Configuration.................................................................................................. 677

18.9.3 Register Configuration.......................................................................................... 677

18.9.4 Operation .............................................................................................................. 683

Section 19 Serial Communication Interface with FIFO (SCIF) .......................... 687

19.1

Overview............................................................................................................................ 687

19.1.1 Features................................................................................................................. 687

19.2

Pin Configuration...............................................................................................................690

19.3

Register Description .......................................................................................................... 691

19.3.1 Receive Shift Register (SCRSR) .......................................................................... 692

19.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 692

19.3.3 Transmit Shift Register (SCTSR) ......................................................................... 692

19.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 693

19.3.5 Serial Mode Register (SCSMR)............................................................................ 693

19.3.6 Serial Control Register (SCSCR).......................................................................... 697

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