SH7710 datasheet(49/996 Pages) RENESAS

49 / 996 page

Section 1 Overview and Pin Function

Rev. 2.00 Dec. 07, 2005 Page 7 of 950

REJ09B0079-0200

1.2

Block Diagram

SuperH

CPU core

X/Y memory

Instructions/data for

CPU/DSP 16 kbytes

User break

controller

(UBC)

DSP core

Cache

access

controller

(CCN)

Direct

memory

access

controller

(DMAC)

Memory

management

unit

(MMU)

Cache

memory

32 kbytes

Bus state

controller

(BSC)

IP security

accelerator

(IPSEC)

Peripheral

bus

controller

Ethernet

controller

direct memory

access

controller

(E-DMAC)

CPU bus (I clock)

Internal bus (B clock)

External bus

Note: * SCIF and SIOF have two channels respectively.

128-byte

SRAM

Serial I/O

with FIFO

(SIOF)*

User

debugging

interface

(H-UDI)

Interrupt

controller

(INTC)

Realtime

clock

(RTC)

Timer

unit

(TMU)

On-chip

oscillation

circuits

(CPG)

(WDT)

Serial

communication

interface

with FIFO

(SCIF)*

Transmit FIFO

(2 kbytes)

Ethernet controller 0

(EtherC0)

Ethernet controller 1

(EtherC1)

Transfer FIFO

(3 kbytes)

Transfer FIFO

(3 kbytes)

Receive FIFO

(2 kbytes)

Transmit FIFO

(2 kbytes)

Receive FIFO

(2 kbytes)

X bus

Y bus

Ethernet 0

Ethernet 1

Peripheral bus (P clock)

Advanced

user

debugger

(AUD)

L bus

Figure 1.1 Block Diagram

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