7540 datasheet(220/366 Pages) RENESAS

220 / 366 page

2-144

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPLICATION

7540 Group

2.9 Reset

Fig. 2.9.11 Control procedure

Notes 1: At VCC = 5 V, the timer A count source when an on-chip oscillator

is selected as the operation clock is as follows;

About 2 MHz / 16 = about 125 kHz

2: When setting the value to timer, set in order of low-order byte

and high-order byte following.

3: 0.5 s = 1/125 kHz ✕ (F42316 + 1)

4: For the concrete time, ask the oscillator manufacture.

Modes 3, 4 (common)

Switch to ceramic

oscillation is required?

RESET

SEI

CLD

CLT

10 0

CLI

WIT instruction executed

Wait mode

Processing

Timer A interrupt processing routine

Processing

10 0

00 0

Processing

10 0

TAM(Address 1D16)

Count stop

Set timer A mode register

RTI

TAM(Address 1D16)

Timer mode selected

Count stop

Set timer A mode register

“2316”

“F416”

Timer A (high-order) [Address 1F16]

Set values to timer A (Notes 2, 3)

Set “0” to the timer A interrupt request bit

Timer A (low-order) [Address 1E16]

Modes 3, 4

Operation mode by ceramic oscillation

Switch to double-speed

mode is required?

RTS

On-chip oscillator oscillation enabled

XIN oscillation (ceramic) stop

Applied from on-chip oscillator

Operation mode by ceramic oscillation

Mode 2

Mode 1

Mode 2

Mode 3

Mode 4

Initialization

Set CPU mode register

CPUM(Address 3B16)

Single-chip mode

On-chip oscillator oscillation enabled

f(XIN) oscillation (ceramic) stop

Ceramic oscillation

Applied from on-chip oscillator (Note 1)

Set CPU mode register

CPUM(Address 3B16)

Set “0” to the timer A interrupt enable bit.

(Timer A interrupt disabled)

Timer A division ratio (fixed)

Timer A setting value

Wait until f(XIN) oscillation is stabilized (Note 4)

Set CPU mode register

CPUM(Address 3B16)

Double-speed mode

Set CPU mode register

CPUM(Address 3B16)

Set CPU mode register

CPUM(Address 3B16)

Set “0” to the timer A interrupt enable bit.

(Timer A interrupt disabled)

Set “0” to other interrupt enable bits.

(Other interrups disabled)

TAM(Address 1D16)

Count start

Set timer A mode register

f(XIN) oscillation (ceramic) enabled

Middle-speed mode

7540 Datasheet(PDF) 220 Page - Renesas Technology Corp

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