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7540 Datasheet(PDF) 216 Page - Renesas Technology Corp |
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7540 Datasheet(HTML) 216 Page - Renesas Technology Corp |
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216 / 366 page ![]() 2-140 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset (2) Setting method Figure 2.9.7 shows the initial setting method oscillation stop detection circuit. Figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing. Fig. 2.9.7 Initial setting method for the oscillation stop detection circuit Process 1: Check that reset by oscillation stop detection is executed by referring the oscillation stop detection status bit. Process 2: Select oscillation mode. b7 b0 MISRG (MISRG) [Address 3816] Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected * Execute the following set at the beginning of program after system is released from reset. 0 0 • Oscillation stop is detected Some error occus in the oscillation circuit. Do not switch the operation clock and execute the processing when some error occurs. • Oscillation stop is not detected Execute the Process 2. b7b0 CPU mode register (CPUM) [Address 3B16] Oscillation mode selection bit (Note) 0: Ceramic oscillation 1: RC oscillation Process 3: Wait oscillation stabilizing (Note). Note: This process can be eliminated when the RC oscillation is selected. For the oscillation stabilizing time, ask the oscillator manufacture. Process 4: Set the ceramic or RC oscillation stop detection function active bit. b7 b0 Detection function active (Note) 0 01 MISRG (MISRG) [Address 3816] Note: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37540RSS”). 0 00 0 0 0 0 0 1 0 00 Note: When some error occurs in the oscillation circuit, system is released from reset after setting of Process 4 is executed. Process 5: Select clock division ratio. b7 b0 CPU mode register (CPUM) [Address 3B16] Clock division ratio selection bits b7b6 0 0: f( φ) = f(XIN)/2 (high-speed mode) 0 1: f( φ)= f(XIN)/8 (middle-speed mode) 1 0: Applied from on-chip oscillator 1 1: f( φ)=f(XIN) (double-speed mode) (Note) Note: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. 0 0 |
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