7540 datasheet(218/366 Pages) RENESAS

218 / 366 page

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REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPLICATION

7540 Group

2.9 Reset

2.9.5 State transition

In the 7540 Group, the operation clock is selected from the following 4 types.

• f(XIN)/2 (high-speed mode)

• f(XIN)/8 (middle-speed mode)

• On-chip oscillator

• f(XIN) (double-speed mode) (Note 1)

Note 1: f(XIN) can be used only at the ceramic oscillation. Do not use f(XIN) at RC oscillation.

Also, in the 7540 Group, the function to stop CPU operation by software and to keep CPU wait in the

following 2-type low power dissipation.

q Stop mode with the STP instruction (Notes 2, 3, 4, 5, 6, 7)

q Wait mode with the WIT instruction (Note 8)

Notes 2: When the stop mode is used, set the oscillation stop detection function to “invalid”.

3: When the stop mode is used, set “0” (STP instruction enabled) the STP instruction disable bit

of the watchdog timer control register.

4: Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The

oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/

“not set automaticallzy” by the oscillation stabilizing time set bit after release of the STP instruction

of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1

automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set

the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is

used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.

5: The STP instruction cannot be used during CPU is operating by the on-chip oscillator.

6: When the stop mode is used, stop the on-chip oscillator oscillation.

7: Do not execute the STP instruction during the A/D conversion.

8: When the wait mode is used, stop the clock except the operation clock source.

Figure 2.9.9 shows the state transition.

Fig. 2.9.9 State transition

Stop modeWait mode

WIT

instruction

Oscillation stop detection circuit valid

CPUM4

←12

MISRG1

←12

Interrupt

STP

instruction

WIT

instruction

Interrupt

MISRG1

←02

CPUM3

←12

CPUM3

←02

CPUM76

←102

CPUM76

←002

012

112

(Note 2)

CPUM4

←02

MISRG1

←12

MISRG1

←02

Reset released

State 1

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator stop

State 2

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator enabled

State 3

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

State 4

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation stop

On-chip oscillator enalbed

Notes on switch of clock

(1) In operation clock source = f(XIN), the following can be

selected for the CPU clock division ratio.

q f(XIN)/2 (high-speed mode)

q f(XIN)/8 (middle-speed mode)

q f(XIN) (double-speed mode, only at a ceramic oscillation)

(2) Execute the state transition state 3 to state 2 or

state 3’ to state 2’ after stabilizing XIN oscillation.

(3) In operation clock source = on-chip oscillator, the middle-

speed mode is selected for the CPU clock division ratio.

(4) When the state transition state 2

→ state 3 → state 4

is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

• CPUM76

→ 102 (State 2 → state 3)

• NOP instruction

• CPUM4

→ 12 (State 3 → state 4)

Double-speed mode at on-chip oscillator: NOP ✕ 3

High-speed mode at on-chip oscillator: NOP ✕ 1

Middle-speed mode at on-chip oscillator: NOP ✕ 0

Reset state

CPUM76

←102

CPUM76

←002

012

112

(Note 2)

State 2’

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator enabled

State 3’

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

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