7540 datasheet(297/366 Pages) RENESAS

297 / 366 page

3-75

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPENDIX

3.3 Notes on use

3.3.3 Notes on Timer

• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).

• When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X.

3.3.4 Notes on Timer A

Notes on using timer A are described below.

(1) Common to all modes

➀ When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A

is read out. Read both registers in order of TAH and TAL following, certainly.

TAH and TAL keep the values until they are read out.

Also, do not write to them during read. In this case, unexpected operation may occur.

➁ When writing data to TAL and TAH even when timer A is operating or stopped, the data are set

to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following,

certainly.

Also, do not read them during write. In this case, unexpected operation may occur.

(2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode

➀ In order to use CNTR1 pin, set “0” to bit 0 of the port P0 direction register (input mode).

➁ In order to use CNTR1 pin, set “1” to bit 7 of the interrupt control register to disable the P00 key-

on wakeup function.

➂ CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”,

the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When

this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input

signal.

However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is

generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

3.3.5 Notes on timer 1

Note on timer 1 is described below.

(1) Notes on set of the oscillation stabilizing time

Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The

oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/

“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction

of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1

automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the

wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used,

set values again to timer 1 and prescaler 1 after system is returned from the stop mode.

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