7540 datasheet(301/366 Pages) RENESAS

301 / 366 page

3-79

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPENDIX

3.3 Notes on use

(5) Common to all modes (timer Y and timer Z)

Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode.

Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”.

Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When

timer is read out while timer is stopped, the value of latch is read. The value of timer can be read

out only while timer is operating.)

3.3.8 Notes on Serial I/O1

Notes on using serial I/O1 are described below.

(1) Notes when selecting clock synchronous serial I/O

➀ When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used.

➁ When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable

bit to “0” (serial I/O1 and transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running

(in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data

is not output). When data is written to the transmit buffer register in this state, data starts to be

shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the

data during internally shifting is output to the TxD1 pin and an operation failure occurs.

➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or

clear the serial I/O1 enable bit to “0” (serial I/O1 disabled).

➃ When the transmit/receive operation is stopped, clear both the transmit enable bit and receive

enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and

reception cannot be stopped.)

q Reason

In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.

If any one of transmission and reception is disabled, a bit error occurs because transmission and

reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,

the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit

disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is

cleared to “0” (serial I/O1 disabled) (same as ➁).

➄ When signals are output from the SRDY1 pin on the reception side by using an external clock, set

all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1”.

➅ When the SRDY1 signal input is used, set the using pin to the input mode before data is written to

the transmit/receive buffer register.

➆ Setup of a serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is selected;

“0” : P12 pin turns into an output pin of a synchronous clock.

“1” : P12 pin turns into an input pin of a synchronous clock.

Setup of a SRDY1 output enable bit (SRDY1) when a clock synchronous serial I/O1 is selected;

“0” : P13 pin can be used as a normal I/O pin.

“1” : P13 pin turns into a SRDY1 output pin.

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