SH7730 datasheet(13/1188 Pages) RENESAS

13 / 1188 page

Rev. 1.00 Sep. 19, 2007 Page xiii of xlviii

Section 9 On-Chip Memory...............................................................................237

9.1

Features............................................................................................................................. 237

9.2

Register Descriptions ........................................................................................................ 238

9.2.1

On-Chip Memory Control Register (RAMCR) ........................................................ 238

9.3

Operation .......................................................................................................................... 240

9.3.1

Instruction Fetch Access from the CPU.................................................................... 240

9.3.2

Operand Access from the CPU and Access from the FPU ....................................... 240

9.3.3

Access from the SuperHyway Bus Master Module .................................................. 240

9.4

On-Chip Memory Protective Functions ............................................................................ 241

9.5

Usage Notes ...................................................................................................................... 242

9.5.1

Page Conflict ............................................................................................................ 242

9.5.2

Access Across Different Pages ................................................................................. 242

9.5.3

On-Chip Memory Coherency ................................................................................... 242

9.5.4

Sleep Mode ............................................................................................................... 242

Section 10 Interrupt Controller (INTC) .............................................................243

10.1

Features............................................................................................................................. 243

10.2

Input/Output Pins.............................................................................................................. 245

10.3

Register Descriptions ........................................................................................................ 245

10.3.1

Interrupt Control Register 0 (ICR0) ....................................................................... 249

10.3.2

Interrupt Control Register 1 (ICR1) ....................................................................... 251

10.3.3

Interrupt Priority Register 00 (INTPRI00) ............................................................. 252

10.3.4

Interrupt Priority Registers A to K (IPRA to IPRK) .............................................. 253

10.3.5

Interrupt Request Register 00 (INTREQ00)........................................................... 254

10.3.6

Interrupt Mask Register 00 (INTMSK00).............................................................. 255

10.3.7

Interrupt Mask Clear Register 00 (INTMSKCLR00)............................................. 256

10.3.8

Interrupt Mask Registers 0 to 12 (IMR0 to IMR12) .............................................. 257

10.3.9

Interrupt Mask Clear Registers 0 to 12 (IMCR0 to IMCR12)................................ 258

10.3.10

User Interrupt Mask Level Register (USERIMASK)............................................. 260

10.3.11

NMI Flag Control Register (NMIFCR).................................................................. 261

10.4

Interrupt Sources...............................................................................................................262

10.4.1

NMI Interrupt ......................................................................................................... 262

10.4.2

IRQ Interrupts ........................................................................................................ 262

10.4.3

IRL Interrupts......................................................................................................... 263

10.4.4

PINT Interrupt........................................................................................................ 264

10.4.5

On-Chip Peripheral Module Interrupts................................................................... 264

10.4.6

Interrupt Exception Handling and Priority ............................................................. 265

10.5

Operation .......................................................................................................................... 268

10.5.1

Interrupt Sequence ................................................................................................. 268

10.5.2

Multiple Interrupts ................................................................................................. 272

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