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SH7730 Datasheet(PDF) 32 Page - Renesas Technology Corp |
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SH7730 Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 1188 page  Rev. 1.00 Sep. 19, 2007 Page xxxii of xlviii Figure 11.33 Basic Access Timing for Byte-Selection SRAM (BAS = 1)................................. 387 Figure 11.34 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)........... 388 Figure 11.35 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............. 389 Figure 11.36 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............. 389 Figure 11.37 Example of PCMCIA Interface Connection.......................................................... 391 Figure 11.38 Basic Access Timing for PCMCIA Memory Card Interface................................. 392 Figure 11.39 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) .............................. 393 Figure 11.40 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10) ................................................................................. 394 Figure 11.41 Basic Timing for PCMCIA I/O Card Interface ..................................................... 396 Figure 11.42 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) .............................. 397 Figure 11.43 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ........................... 397 Figure 11.44 Bus Arbitration Timing ......................................................................................... 400 Section 12 Direct Memory Access Controller (DMAC) Figure 12.1 Block Diagram of DMAC ....................................................................................... 404 Figure 12.2 Round-Robin Mode................................................................................................. 432 Figure 12.3 Changes in Channel Priority in Round-Robin Mode............................................... 433 Figure 12.4 Data Flow of Dual Address Mode........................................................................... 435 Figure 12.5 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) ................................ 436 Figure 12.6 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)......................................................... 437 Figure 12.7 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection)......................................................... 438 Figure 12.8 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)......................................................... 438 Figure 12.9 Bus State when Multiple Channels are Operating................................................... 440 Figure 12.10 DMA Transfer Flowchart...................................................................................... 442 Figure 12.11 Reload Mode Transfer........................................................................................... 444 Figure 12.12 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 445 Figure 12.13 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 445 Figure 12.14 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 446 Figure 12.15 Example of DREQ Input Detection in Burst Mode Level Detection .................... 446 Figure 12.16 DMA Transfer End Signal Timing (Level Detection in Cycle Steal Mode) ......... 447 Figure 12.17 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)..................................................................... 447 |
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