SH7764 datasheet(22/1752 Pages) RENESAS

22 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xxii of lvi

20.2.15 Receive Buffer Write Address Register (RBWAR).............................................. 777

20.2.16 Receive Descriptor Fetch Address Register (RDFAR)......................................... 778

20.2.17 Transmit Buffer Read Address Register (TBRAR) .............................................. 779

20.2.18 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 780

20.2.19 Flow Control Start FIFO Threshold Setting Register (FCFTR) ........................... 781

20.2.20 Receive Data Padding Insert Register (RPADIR) ................................................ 783

20.2.21 Transmit Interrupt Setting Register (TRIMD) ...................................................... 784

20.2.22 Independent Output Signal Setting Register (IOSR) ............................................ 785

20.3

Operation ........................................................................................................................... 786

20.3.1 Descriptor Lists and Data Buffers......................................................................... 786

20.3.2 Transmission......................................................................................................... 795

20.3.3 Reception .............................................................................................................. 797

20.3.4 Transmit/Receive Processing of Multi-Buffer Frame

(Single-Frame/ Multi-Descriptor)......................................................................... 799

Section 21 USB 2.0 Host/Function Module (USB)........................................... 801

21.1

Features.............................................................................................................................. 801

21.2

Input / Output Pins.............................................................................................................804

21.3

Register Description .......................................................................................................... 805

21.3.1 System Configuration Control Register (SYSCFG) ............................................. 811

21.3.2 CPU Bus Wait Setting Register (BUSWAIT) ...................................................... 815

21.3.3 System Configuration Status Register (SYSSTS)................................................. 816

21.3.4 Device State Control Register (DVSTCTR) ......................................................... 818

21.3.5 Test Mode Register (TESTMODE) ...................................................................... 823

21.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) .................... 826

21.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) ................................................ 827

21.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)................. 830

21.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ............ 837

21.3.10 Interrupts Enable Register 0 (INTENB0) ............................................................. 841

21.3.11 Interrupt Enable Register 1 (INTENB1)............................................................... 843

21.3.12 BRDY Interrupt Enable Register (BRDYENB) ................................................... 845

21.3.13 NRDY Interrupt Enable Register (NRDYENB) ................................................... 847

21.3.14 BEMP Interrupt Enable Register (BEMPENB).................................................... 849

21.3.15 SOF Control Register (SOFCFG) ......................................................................... 851

21.3.16 Interrupt Status Register 0 (INTSTS0) ................................................................. 852

21.3.17 Interrupt Status Register 1 (INTSTS1) ................................................................. 858

21.3.18 BRDY Interrupt Status Register (BRDYSTS)...................................................... 864

21.3.19 NRDY Interrupt Status Register (NRDYSTS) ..................................................... 866

21.3.20 BEMP Interrupt Status Register (BEMPSTS) ...................................................... 868

21.3.21 Frame Number Register (FRMNUM) .................................................................. 869

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