SH7764 datasheet(30/1752 Pages) RENESAS

30 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xxx of lvi

30.2.9 Break Control Register (CBCR) ......................................................................... 1460

30.3

Operation Description...................................................................................................... 1461

30.3.1 Definition of Words Related to Accesses ........................................................... 1461

30.3.2 User Break Operation Sequence ......................................................................... 1461

30.3.3 Instruction Fetch Cycle Break ............................................................................ 1462

30.3.4 Operand Access Cycle Break ............................................................................. 1464

30.3.5 Sequential Break ................................................................................................. 1465

30.3.6 Program Counter Value to be Saved................................................................... 1467

30.4

User Break Debugging Support Function ........................................................................ 1468

30.5

User Break Examples....................................................................................................... 1470

30.6

Usage Notes ..................................................................................................................... 1474

Section 31 User Debugging Interface (H-UDI)............................................... 1477

31.1

Features............................................................................................................................ 1477

31.2

Input/Output Pins............................................................................................................. 1479

31.3

Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD,

BYPASS, CLAMP and HIGHZ) ..................................................................................... 1480

31.4

Register Descriptions ....................................................................................................... 1482

31.4.1 Instruction Register (SDIR) ................................................................................ 1483

31.4.2 Interrupt Source Register (SDINT)..................................................................... 1484

31.4.3 Bypass Register (SDBPR) .................................................................................. 1485

31.4.4 Boundary Scan Register (SDBSR) ..................................................................... 1485

31.5

Operation ......................................................................................................................... 1506

31.5.1 TAP Control ....................................................................................................... 1506

31.5.2 H-UDI Reset ....................................................................................................... 1507

31.5.3 H-UDI Interrupt .................................................................................................. 1507

31.6

Usage Notes ..................................................................................................................... 1507

Section 32 List of Registers............................................................................. 1509

32.1

Register Addresses........................................................................................................... 1509

32.2

Section 33 Electrical Characteristics ............................................................... 1573

33.1

Absolute Maximum Ratings ............................................................................................ 1573

33.2

Power-on/Power-off Sequence ........................................................................................ 1574

33.3

DC Characteristics ........................................................................................................... 1575

33.4

AC Characteristics ........................................................................................................... 1581

33.4.1 Clock and Control Signal Timing ....................................................................... 1581

33.4.2 Control Signal Timing ........................................................................................ 1584

33.4.3 Bus Timing ......................................................................................................... 1586

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