SH7764 datasheet(23/1752 Pages) RENESAS

23 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xxiii of lvi

21.3.22

µFrame Number Register (UFRMNUM) ............................................................. 872

21.3.23 USB Address Register (USBADDR).................................................................... 873

21.3.24 USB Request Type Register (USBREQ) .............................................................. 874

21.3.25 USB Request Value Register (USBVAL)............................................................. 876

21.3.26 USB Request Index Register (USBINDX) ........................................................... 877

21.3.27 USB Request Length Register (USBLENG) ........................................................ 878

21.3.28 DCP Configuration Register (DCPCFG) .............................................................. 879

21.3.29 DCP Maximum Packet Size Register (DCPMAXP)............................................. 880

21.3.30 DCP Control Register (DCPCTR) ........................................................................ 881

21.3.31 Pipe Window Select Register (PIPESEL)............................................................. 891

21.3.32 Pipe Configuration Register (PIPECFG) .............................................................. 892

21.3.33 Pipe Buffer Setting Register (PIPEBUF).............................................................. 899

21.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)............................................. 902

21.3.35 Pipe Timing Control Register (PIPEPERI)........................................................... 904

21.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)............................................... 906

21.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)............... 926

21.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) .......................... 928

21.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A)................. 930

21.4

Operation ........................................................................................................................... 933

21.4.1 System Control and Oscillation Control ............................................................... 933

21.4.2 Interrupt Functions................................................................................................ 935

21.4.3 Pipe Control .......................................................................................................... 959

21.4.4 FIFO Buffer Memory............................................................................................ 969

21.4.5 Control Transfers (DCP)....................................................................................... 979

21.4.6 Bulk Transfers (PIPE1 to PIPE5).......................................................................... 983

21.4.7 Interrupt Transfers (PIPE6 to PIPE9) ................................................................... 985

21.4.8 Isochronous Transfers (PIPE1 and PIPE2) ........................................................... 986

21.4.9 SOF Interpolation Function .................................................................................. 997

21.4.10 Pipe Schedule........................................................................................................ 998

21.5

Usage Notes ..................................................................................................................... 1000

21.5.1 USB Startup and Stop Procedures ...................................................................... 1000

Section 22 LCD Controller (LCDC)................................................................1001

22.1

Features............................................................................................................................ 1001

22.2

Input/Output Pins ............................................................................................................. 1003

22.3

Register Configuration..................................................................................................... 1004

22.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1007

22.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1009

22.3.3 LCDC Data Format Register (LDDFR).............................................................. 1012

22.3.4 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1014

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