7220 datasheet(122/303 Pages) RENESAS

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2-95

7220 Group User’s Manual

2.15 Reset

Fig. 2.15.1 Timing diagram at reset

2.15 Reset

To reset the microcomputer, applied LOW level to pin RESET for 2

µs or more. Reset is released when

HIGH level is applied to pin RESET, and the program starts from the address indicated with the reset vector

table.

2.15.1 Reset operation

If pin RESET is returned to an HIGH level after being held LOW for 2

µs or more when the power source

voltage is within the recommended range (4.5 V to 5.5 V), timers 3 and 4 are connected by hardware with

internally reset state (internal timing signal

φ is not supplied).

At this time, “FF16” is set to timer 3, and “0716” is set to timer 4. Timer 3 counts down f(XIN)/16 as its count

source; timer 4 counts down the timer 3 overflow signal (even when the device is in internally reset state,

f(XIN) is continuously supplied to timer 3).

The internal reset is released by timer 4 overflow, and the program is started from an address determined

with the contents of address FFFF16 (as high-order address) and contents of address FFFE16 (as low-order

address). Figure 2.15.1 shows this sequence.

ADH,

ADL

01,S–2

01,S–1

PCH

PCL

ADH

ADL

01,S

FFFE16

FFFF16

SYNC

Address

Data

RESET

Internal

reset

XIN

Notes 1: f(XIN) and f(

φ) are in the relation : f(XIN) = 2•f(φ).

2: A question mark (?) indicates an undefined state that depends on the previous state.

3: Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16”

is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset

state is released by the timer 4 overflow signal.

32,768 counts of f(XIN) by

timers 3 and 4

FUNCTIONAL DESCRIPTION

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