H83069RF datasheet(144/1003 Pages) RENESAS

144 / 1003 page

Rev. 5.0, 09/04, page 122 of 978

Bit 5—Address 21 Enable (A21E): Enables PA

6 to be used as the A21 address output pin.

Writing 0 in this bit enables A

21 output from PA6.

In modes other than 3, 4, and 5, this bit cannot

be modified and PA

6 has its ordinary port functions.

Bit 5

A21E

Description

0PA

6 is the A21 address output pin

1PA

6 is an input/output pin

(Initial value)

Bit 4—Address 20 Enable (A20E): Enables PA

7 to be used as the A20 address output pin.

Writing 0 in this bit enables A

20 output from PA7.

This bit can only be modified in mode 5.

Bit 4

A20E

Description

0PA

7 is the A20 address output pin (Initial value when in mode 3 or 4)

1PA

7 is an input/output pin (Initial value when in mode 1, 2, 5, or 7)

Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.

Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.

Bit 0

BRLE

Description

The bus cannot be released to an external device

BREQ and BACK can be used as input/output pins

(Initial value)

The bus can be released to an external device

6.2.5

Bus Control Register (BCR)

BRSTS0

EMC

RDEA

WAITE

Initial value

0110

Read/Write

R/W

765

3210

ICIS1

ICIS0

BROME BRSTS1

Bit

BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the

address map, selects the area division unit, and enables or disables

WAIT pin input.

BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

H83069RF Datasheet(PDF) 144 Page - Renesas Technology Corp

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