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H83069RF Datasheet(PDF) 147 Page - Renesas Technology Corp |
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H83069RF Datasheet(HTML) 147 Page - Renesas Technology Corp |
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147 / 1003 page ![]() Rev. 5.0, 09/04, page 125 of 978 When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer to appendix B.2, Addresses (EMC = 0). When the RDEA bit is 0, EMC must not be cleared to 0. Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, and 7. When the EMC bit is 0, RDEA must not be cleared to 0. Bit 1 RDEA Description 0 Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes Area 1: 2 Mbytes Area 5: 4 kbytes Area 2: 8 Mbytes Area 6: 23.75 kbytes Area 3: 2 Mbytes Area 7: 22 bytes 1 Areas 0 to 7 are the same size (2 Mbytes) (Initial value) Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description 0 WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) 1 WAIT pin wait input is enabled |
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