H83069RF datasheet(149/1003 Pages) RENESAS

149 / 1003 page

Rev. 5.0, 09/04, page 127 of 978

6.2.7

DRAM Control Register A (DRCRA)

RDM

SRFMD

RFSHE

Initial value

Read/Write

R/W

—

76543210

DRAS2

DRAS1

DRAS0

—

Bit

DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface

function, and the access mode, and enables or disables self-refreshing and refresh pin output.

DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are

to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time

select the

RAS output pin corresponding to each DRAM space.

Description

Bit 7

DRAS2

Bit 6

DRAS1

Bit 5

DRAS0 Area 5

Area 4

Area 3

Area 2

Normal

DRAM space

(

Normal

DRAM space

(

DRAM space

(

Normal

DRAM space

(

2)*

DRAM space

(

2)*

Normal

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

4)*

DRAM space

(

4)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

Note:

A single

CSn pin serves as a common RAS output pin for a number of areas. Unused

CSn pins can be used as input/output ports.

When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to

DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in

RTMCSR to clear the flag.

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