H83069RF datasheet(178/1003 Pages) RENESAS

178 / 1003 page

Rev. 5.0, 09/04, page 156 of 978

Table 6.5

Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (

RAS

Output Pin)

DRAS2 DRAS1 DRAS0 Area 5

Area 4

Area 3

Area 2

Normal space

DRAM space

(

Normal space

DRAM space

(

DRAM space

(

Normal space

DRAM space

(

2)*

DRAM space

(

2)*

Normal space

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

4)*

DRAM space

(

4)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

DRAM space

(

2)*

Note:

A single

n pin serves as a common RAS output pin for a number of areas.

Unused

n pins can be used as input/output ports.

6.5.3

Address Multiplexing

When DRAM space is accessed, the row address and column address are multiplexed. The

address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the

number of bits in the DRAM column address. Table 6.6 shows the correspondence between the

settings of MXC1 and MXC0 and the address multiplexing method.

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