H83069RF datasheet(209/1003 Pages) RENESAS

209 / 1003 page

Rev. 5.0, 09/04, page 187 of 978

In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from

ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

Data bus

094

Address bus

Data bus

094

Bus cycle A Bus cycle B

Long buffer-off

time

Data

collision

(a) Idle cycle not inserted

(b) Idle cycle inserted

Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1)

External Address Space Access Immediately after DRAM Space Access: If a DRAM space

access is followed by a non-DRAM external access when

HWR and LWR have been selected as

the

UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a T

i cycle is inserted

regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the

operation.

This is done to prevent simultaneous changing of the

HWR and LWR signals used as UCAS and

LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to

the external device in the next cycle.

A T

i cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output

pins.

In the case of consecutive DRAM space access precharge cycles (T

p), the ICIS0 bit settings are

invalid. In the case of consecutive reads between different areas, for example, if the second

access is a DRAM access, only a T

p cycle is inserted, and a Ti cycle is not.

The timing in this case

is shown in figure 6.46.

H83069RF Datasheet(PDF) 209 Page - Renesas Technology Corp