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H83069RF Datasheet(PDF) 216 Page - Renesas Technology Corp |
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H83069RF Datasheet(HTML) 216 Page - Renesas Technology Corp |
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216 / 1003 page  Rev. 5.0, 09/04, page 194 of 978 BRCR Write Timing: Data written to BRCR to switch between A 23, A22, A21, or A20 output and generic input or output takes effect starting from the T 3 state of the BRCR write cycle. Figure 6.51 shows the timing when a pin is changed from generic input to A 23, A22, A21, or A20 output. φ T1 T2 T3 PA7 to PA4 (A23 to A20) Address bus BRCR address High-impedance Figure 6.51 BRCR Write Timing 6.11.2 BREQ BREQ BREQ BREQ Pin Input Timing After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly. |
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